Raster scanning circuits of television receivers are synchronized to the synchronizing component or sync of the received video signal, which includes horizontal and vertical synchronizing components delineating horizontal lines and vertical fields. The standard NTSC video signal, for example, is defined by two successive fields of 262.5 horizontal lines each, at a horizontal line frequency of 15,734 Hz, designated fH or 1 fH or 1 H. The horizontal lines of the two fields are interlaced by successive display to form a complete 525 line video frame that recurs at a 29.97 Hz rate.
Efforts to improve the picture quality of television receivers have included the development of progressively scanned or noninterlaced display systems in which a full frame of 525 lines is displayed during the time allotted for one 262.5 line field in the video signal. This requires that the horizontal lines be scanned at a display frequency equal to twice the video signal frequency, or 2 fH, while operating in sync with the video signal. It is necessary for such a television receiver to generate a horizontal triggering signal at a display frequency that is twice the horizontal frequency of the video signal, effectively inserting horizontal triggering pulses precisely between the pulses obtained from the input sync signal. Similarly, one might display a 1 fH video signal at some other multiple of the video signal frequency. For example, a 1 fH or 2 fH video signal could be displayed at a 4 fH display scanning frequency, or another multiple could be used.
A circuit for generating a display frequency signal advantageously involves a multiplying phase locked loop that tracks the synchronizing component of the received input signal. In a multiplying phase locked loop, for example, to develop horizontal triggering signals locked to a received video signal, a voltage controlled oscillator is typically operated at a frequency that is some multiple of the input signal. The output of the voltage controlled oscillator is counted down by that multiple, namely to 1 fH, for example, using one or more counters or flip-flops as a frequency divider. The counted down 1 fH signal from the frequency divider is fed back to a phase comparator that is responsive to the synchronizing component of the video signal and generates an output voltage as a function of the phase alignment between the synchronizing component of the video signal and the oscillator. The output of the phase comparator provides a tuning voltage for controlling the frequency of the oscillator, enabling the television receiver to seek and lock onto the synchronizing component of the video signal.
Assuming the input video signal is stable, the phase comparator generates a tuning voltage when the loop is locked, where the average or direct current component of the tuning voltage is stable. The tuning voltage, however, may vary periodically at the rate of the synchronizing signal, e.g. in a ramp or sawtooth manner, depending upon the circuit used to filter the tuning voltage. The sawtooth modulates the oscillator output frequency within the period of the synchronizing input signal, even though the counted down 1 fH signal is held correctly in phase with the video synchronizing signal. A triggering signal can be generated from such a circuit at a multiple of the 1 fH signal by tapping at a point in the frequency divider chain that produces an output at a frequency higher than the 1 fH feedback signal that is the basis of phase locking control. Undesirably, pulses at such higher frequency will not occur symmetrically between pulses at the controlled 1 fH frequency because of the sawtooth modulation of the oscillator frequency introduced by the AC component of the tuning voltage.
The effect of such periodic variations in the oscillator frequency may be appreciated in connection with an example wherein the voltage controlled oscillator operates at 32 fH. The oscillator output is frequency divided by 32 to produce a 1 fH feedback signal to the phase comparator. The oscillator frequency is divided by 16 to provide a 2 fH signal for controlling deflection circuitry used for noninterlaced horizontal scanning. When the 32 fH output frequency varies during a 1 fH cycle due to tuning voltage modulation, alternate horizontal lines at 2 fH will be of unequal length. A tearing effect is produced in the display because alternate lines are of different lengths and are not vertically aligned. Resonance effects of the deflection circuitry tend to enhance this tearing effect, which is highly undesirable in a noninterlaced display.
The phase comparator output is typically coupled to the oscillator through a low pass filter that can reduce the extent to which the oscillator output frequency is modulated at a 1 fH rate. However, extensive filtering reduces the response and tracking ability of the phase locked loop. Additionally, a plurality of phase locked loops may be cascaded, where a first phase locked loop generates a 2 fH triggering signal from the synchronizing input signal and a second phase locked loop associated with the deflection circuit synchronizes scanning to the generated 2 fH triggering signal. However, there are conflicting requirements on the two phase locked loops, and sufficient attenuation of the 1 fH component may not be achievable without sacrificing some other system parameter.